Failure Analysis Delayer

Chip Failure Analysis

Chip failure analysis is mainly applied to improve yield enhancement and reverse engineering of chips, including chip decapping, passivation/insulation layer removal (Delayer), aluminum/copper wire removal, adhesive layer removal, backside silicon access and other specific technical means. Delayer technology requires the complete removal of the insulation layer between metal lines, exposing the next layer of metal lines appropriately, and sometimes preserving the via holes between metal lines and removing the adhesive layer, which is a challenging technology in failure analysis.

We have developed a reaction ion etching machine (SHL FA100/150/200 RIE/ICP) specifically designed for failure analysis, based on the specific requirements of users. The process stability is adjusted to the optimal state, while considering the convenience of operation, allowing users to complete the specified process with one click. The entire process system is fully automated, and this series of machines has been recognized by a large number of industry users; Mainly used for SiO2/SiNx delamination, Backstide Silicon Access, etc; At the same time, we have also developed a physical etching machine for metal layers (SHL FA100/150/200 IBE).

RIE, ICP-RIE, and IBE machines suitable for failure analysis

The main functions of reactive ion etching (RIE for FA) are:

1. Delayer the passivation insulation layer SiO2/SiNx;

2. Minimum nodes that can be processed: 20 nm;

3. Etching rate: 50~300 nm/min;

4. Etching surface roughness<1 nm;

5. Etching uniformity<5%;

6. For Cu/Al selection ratio>50;

The main functions of inductively coupled plasma etching (ICP for FA) are:

1. SiO2/SiNx delamination, Al/Cu delamination, and Backstide Silicon Access;

2. Minimum nodes that can be processed: 20 nm;

3. Etching rate:

SiO2/SiNx: 50 ~ 500 nm/min

Al: 100 ~ 300 nm/min

Cu: 5 ~ 20 nm/min

Si: 500 ~ 4000 nm/min

4. Etching surface roughness<5 nm;

5. Etching uniformity<5%;

The main functions of inductively coupled plasma etching (ICP for FA) are:

1. Delayer of metal Al/Cu;

2. Minimum nodes that can be processed: 20 nm;

3. Etching rate 5~50 nm/min;

4. Etching surface roughness<5 nm;

5. Etching uniformity<5%;

6. Selection ratio of SiO2/SiNx~1;

Application results of chip failure analysis etching machine:

Passivation layer with holes and layer removal etching (SEM)

Passivation layer with holes and layer removal etching (SEM)

Passivation layer with holes and layer removal etching (SEM)

Passivation layer with holes and layer removal etching (SEM)

Passivation layer with holes and layer removal etching (SEM)

Passivation layer with holes and layer removal etching (SEM)

Passivation layer removal etching (OM)

Passivation layer with holes and layer removal etching (SEM)

M2 layer unprocessed                                M2 layer processed

M6 layer unprocessed                                M6 layer processed

M7 layer unprocessed                                M7 layer processed

SHL 200SV-RIE